In the art, there are three systems to which the present invention can be compared: (1) IBM's Test Coverage Estimation tool; (2) Verilog's profiling capacity; and (3) general prior art profiling techniques in use for software testing.
In the below discussion, the term `profiling` will be used to designate the practice of surrounding existing computer code of a high-level language program (such as a C program or PASCAL program) with what we have previously termed `monitor code`. In other words, profiling is synonymous with what we have defined `instrumenting` or `instrumentation` to be in the text below.
IBM has developed a software tool for estimating test coverage during simulation. However, their tool does not have the ability to parse through the model being simulated and to search out logic expressions that need to be satisfied for `completeness`. The IBM tool cannot be used to determine if desired combinations of logic values have occurred on predetermined circuit nodes during simulation. Furthermore, the IBM tool does not have a model for fault test controllability, and cannot perform the checks for fault-controllability. Nor does it have a model for functional test completeness or reduction of test vectors to reduce testing clock cycles and maximize test coverage. The IBM test coverage estimation tool is limited to checking for execution of certain lines of code during a simulation, and for the `toggling` of certain assignment variables (i.e., checking if those variables were put in both the true and false logic states during a simulation). The IBM tool does not go beyond this capability, to the generation of code for automatic checking of the satisfaction of logic expressions pertinent to fault-controllability. The IBM test tool also cannot be used to check for functional test completeness.
Verilog simulators have the ability to output information as to line execution rates; however, they have no ability to output information on toggling of variables, nor about combinations of circuit nodes asserted, nor about sequences of circuit combinations asserted. Also, a Verilog simulator is used only if one uses Verilog as the hardware description language (hereafter HDL). A Verilog simulator cannot take any HDL as input and, with appropriate adaptation, make that HDL work in concert with any simulator.
General profiling techniques are used for software for code instrumentation (i.e., generation of additional code to check for the occurrence of various events) is used. However, the types of checks made by a software profiling package are different from the tests, hardware, and algorithms needed to perform test coverage estimation. Mostly, software profilers tabulate line execution rates, and check to make sure the code takes both the true and false branches through conditional clauses (e.g. an if-then-else construct).